Branch Target Address

Question

In a normal 5-stage pipeline, when is the branch target address available?

There are some sources which say that the address is available after the MEM stage, but go on to say that it can be found out after the ID stage if we put in an extra adder.

GATE13 had a question in which they assumed that the address is available after the 4^th stage. Is that the approach to be followed for all the questions?

 

Answer 1

1. If in the question it is given it is a branch instruction and the branch prediction technique gives correct output, then branch penalty=0;

2. If it is given that branch instruction cannot start until the current execution, then it will start after WB stage and so number of stalls=branch penalty will be 4(IF of next  instruction  will start after WB of the branch instruction).

3.If it is given it will start after M then branch penalty will be 3(IF of next  instruction  will start after M of the branch instruction).

Hope this clears your doubt.I almost cover all the cases.