GATE ECE digital logic

Question

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________

Comments

to calculate s15  we have to take all the carry from C0 to C14 =15*12(carry delay)+ S15(15 given for sum delay )

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ok but why are u not taking into account sum delay of FF0-FF14?

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sum delay is not required, s15 can be calculated using the c0-c14 and s15 will take more delay among all the others.in s15 time u can calculate all the other sum s1,s2 etc.so worst case delay is calculating s15.

Answer 1

First carry produced at 12 ns sum at 15

Second carry at 24 . Sum at 12 +15=27

Third carry at 36 sum at 24 + 15=39

4th carry at  48 sum at 36 +15=51

Till now, time taken is 51 =3*12 +15

Similarly for 16 =15*12 +15=195