ME TEST SERIES

Question

A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is ________.

100, 108, 114, 1C7, 128, 1B5, 100, 108, 1C7

Comments

@aambazinga Thanks! for the confirmation

 

---

@Shaik Masthan brother this is the solution they given

---

offset should be 4 bits ===> their answer should be wrong

Answer 1

Attached by aambazinga

 

Comments

@Vishal Kumar 2

what is the block associated with (108)$_H$ ?

if you know this, then you can understand why it is hit !

---

@MiNiPanda

@Prateek Raghuvanshi

@Shaik Masthan

when there is no miss, from which to which address r u taking for it?

I mean when there is a hit , how do u know , upto which block there is a hit

---

and how 1C7 can be replaced by 100?