AAI JE (IT) 2018 - Q74

Question

How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand. 

Comments

1 for instruction fetch and 1 for operand fetch

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@Priyanka Agarwal No!

Answer 1

Decode Stage: During this stage the encoded instruction present in the instruction register is interpreted by the decoder.

• Read the effective address: In the case of a memory instruction (direct or indirect) the execution phase will be during the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers (clock pulse: T3). If the instruction is direct, nothing is done during this clock pulse. If this is an I/O instruction or a register instruction, the operation is performed during the clock pulse.

Answer 2

2 Memory references are required here.

It is Basically an Indirect Addressing Mode. 

EA= [Address Field Value] → [Reg. name (R3)] → [Data (Operand)]