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consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and there are 1.8 memory references per instruction, then average stall per instruction is                  

  1. 6.36
  2. 7.92
  3. 9.62
  4. 9.35
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Easiest solution would be:

calculate the total no of clocks without any miss = [ 2000(5) ]*1.8 = 18000

calculate the same with misses as given in the question = [ 2000(5)  + 80(30) + 40(200) ]*1.8 = 36720

stall cycle per instruction would be 36720 - 18000 / 2000 = 9.36

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Average memory stall time per instruction  =  Average number of memory accesses per instruction * Average memory access time.

Assuming no memory stalls for $L_1$ hit

$L_1$ miss rate $=\frac{80}{2000 \times 1.8} =  \frac{1}{45}$

$L_2$ miss rate $= \frac{40}{80} = 0.5$

Therefore, Average memory stalls time per instruction

$\qquad =1.8 \times  (\frac{1}{45} \times (30 + 0.5 \times 200)$

$\qquad = 1.8 \times \left( \frac{130}{45}\right) = 5.2$ cycles
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