The Gateway to Computer Science Excellence
0 votes
142 views
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Show how cache interprets the processor’s addresses.
in CO and Architecture by (313 points) | 142 views
0
TAG bits : 13 bits

set offset : 10 bits

word offset : 1 bit
0

Does this given solution makes any sense to you? It gives: 12-10-2. I have doubt especially for that word and byte select. Only diagram was given. No explanation πŸ˜‘πŸ˜ž

0
I understood the diagram but what I don't understand is why they have an extra bit as byte select.

When physical address is given, its a reference to word not byte.
0
yup same doubt

Please log in or register to answer this question.

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,834 questions
57,821 answers
199,496 comments
108,303 users