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Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?

in CO and Architecture by Loyal (7.3k points)
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+1

@aambazinga

I don't have any solution :( I am not understanding this solution.

$ Execution-time= \frac{n* CPI}{frequency}= n* CPI* cycle time $

Here cycle time per instruction in non-pipeline is my doubt. If its 26 ns then in 1 cycle only we can execute 1 instruction i.e. CPI=1 which means pipeline efficiency has been achieved in non-pipelining system :/

 

+2
made easy shatters the concepts. i don't agree with this solution at all.
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Same here... :(

@MiNiPanda

That exactly my doubt also

0
+2

i.e. CPI=1 which means pipeline efficiency has been achieved in non-pipelining system :/

@MiNiPanda bro what my understanding is , it is not this way..in above gate question also CPI = 1 for non pipelining

it doesn't mean non pipelinig is effiecient as pipeline ..ultimate goal of pipeline is MAX throughput ..here in both case time for clocks will be different in both Non pipe and pipe. For pipe Cycle time < Cycle time for non pipe hence pipelining is always better than non pipe for large no of instructions in terms of throughput ..number of instructions per sec even though both have CPI = 1

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@jatin khachane 1

Okay..thanks for the link..Didn't know that by default we have to take CPI=1 for non-pipelined organization as well :O

But whats confusing me is, if cycle time is taken to be 26ns, then it means CPI=1.. then what are we calculating? :/

+1

@MiNiPanda

If its 26 ns then in 1 cycle only we can execute 1 instruction i.e. CPI=1

CPI is equals to 1 under ideal condition, not always.

in general, some instructions take 1 cycle, some more than 1.

that's why the question is asking about average CPI.

average CPI of NON-PIPELINE CPU

 and for 

what are we calculating? 

 we are calculating AVERAGE CPI.

0

@aambazinga

Thank you..I  more or less understand it now.. :)

I still find this question a bit doubtful..if under ideal condition CPI=1 then all the instructions executed in that same machine will be under the same ideal condition right..?

0

@MiNiPanda

Yes also got cpi = 1 as answer at first place :)

And we should not consider cpi =1 for non pipeline by default..it is possible only when cycle time = sum of all stages

They may give cpi for non pipeline>1 and some other clock freq which has less cycle time than sum of delays..at the end one instruction take sum of all stages delay time..that may be in more than one clock..

+1

 

A non pipelined single cycle processor operating at  100MHZ.

question explicitly mentioned SINGLE CYCLE here

0
in above gate question asnwer would have been same ..

IF for non-pipeline CPI = 2 and clock frequency = 200MHz
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finally what you concluded for this question ?

for me, the explanation given by @aambazinga and @Gokulnath  given is correct.

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No bro...how can cpi= 1.23 by considering time period of clock for non pipeline as some of all stage delays..for instruction on non pipeline it takes sum of all stage delays ..now if we set clock time as this much..then 1 clock needed for 1 instruction right..
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how can you say, by seeing the clock time, it takes CPI = 1 ?

i mean to say, it is depend upon the instructions., for a non-pipelined model CPI can be more than 1.

But if we change the clock time to large enough, then it take CPI = 1.

( ideally what we think is clock time (sum of all buffers) should produce CPI = 1 )

But in this question, they given the speedup, so you can't say clock time ( sum of all buffers ) should produce 1 instruction i.e., CPI = 1.
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In solution they have considered time period of clock for non pipeline as sum of all stage delays
+1
yes, by taking that as clk, you can't assure CPI = 1

if speedup not given, then you can assume it, but they given speed up and asking CPI, then how can you assume CPI = 1 ?
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M very much confused now :(

Can you explain this bit more...how we cant be sure that 1 instruction takes 1 clock on non pipeline processor ..if tclock= sum of all stage delays ...
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If u got some new concept plz comment so that i cn also understand
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for whom you are asking ?

mention their name in the comment
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3 Answers

+1 vote

Tn= time for non pipelined processor . i.e., sum of all stages delay= 26

Tp= time for a pipelined processor . i.e., highest delay of all the stages = 8

speedup = (Tn * CPI) / (Tp * CPI)

CPI for pipelined processor is 1(ideal case)

let CPI for non pipelined processor = x

speedup = 26x/8

4=26x/8

x=32/26

=1.23

by (175 points)
0 votes

1.23 is right.

 

by Boss (35.7k points)
0 votes
Nothing is given about #instructions or value of n.

In that we should consider $n$ = infinity.

So Speedup for n = infinity is  $S$ = $\frac{T_{n}}{t_{p}}$

or we can write like, $S$ = $\frac{k.t_{n}}{t_{p}}$

Now this k tells us the number of stage or k is nothing but no. of cycles required in Non-pipelined processor, which is CPI.

$t_{n}$ is the cycle time.

So, $4$ = $\frac{CPI*(3+8+5+6+4)}{Max(3,8,5,6,4)}$

solving this eqn, we'll get CPI = 1.23
by Active (3.1k points)

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