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4 votes
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Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?
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5 votes

Tn= time for non pipelined processor . i.e., sum of all stages delay= 26

Tp= time for a pipelined processor . i.e., highest delay of all the stages = 8

speedup = (Tn * CPI) / (Tp * CPI)

CPI for pipelined processor is 1(ideal case)

let CPI for non pipelined processor = x

speedup = 26x/8

4=26x/8

x=32/26

=1.23

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Nothing is given about #instructions or value of n.

In that we should consider $n$ = infinity.

So Speedup for n = infinity is  $S$ = $\frac{T_{n}}{t_{p}}$

or we can write like, $S$ = $\frac{k.t_{n}}{t_{p}}$

Now this k tells us the number of stage or k is nothing but no. of cycles required in Non-pipelined processor, which is CPI.

$t_{n}$ is the cycle time.

So, $4$ = $\frac{CPI*(3+8+5+6+4)}{Max(3,8,5,6,4)}$

solving this eqn, we'll get CPI = 1.23

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