1,993 views
0 votes
0 votes
A pipelined Processor contains 5 instructions stages of execution times 120ns, 160ns, 105 ns, 135ns and 155ns with a register delay 10ns on each stage. What is the percentage of performance increased with 1000 instructions instead of 10 instructions

1 Answer

Best answer
5 votes
5 votes

T np = 120+160+105+1135+155 = 675 ns (nonpipeline )

Tp = 160+10 = 170ns   (pipeline)  [Tp = max(stage delay) +buffer ]

............................................................................................................................

performance gain = speed up = performance pipe / performance nonpipe

                                                 =Effective Time nonpipe / EffectiveTime pipe

                                                = n *Tnp / (k+n-1) * Tp

.............................................................................................................................

case 1 : for n=10 , k=5 

             P1= 10*675 / 14* 170 = 2.836

case 2 : n=1000 , k=5

            P2= 1000*675 /1004 *170= 3.954

............................................................................................................................

%gain = (P1-P2)/ P1 *100 % = 3.954-2.836/ 2.836  *100% =39.4%  answer

selected by

Related questions

0 votes
0 votes
1 answer
1
shima abdullah asked Jun 27, 2022
811 views
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the ...
2 votes
2 votes
2 answers
2
Nihal Singh asked Oct 26, 2021
1,436 views
Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?
1 votes
1 votes
1 answer
3
s_dr_13 asked Mar 8, 2019
652 views
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE