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Shadan Karim
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CO and Architecture
Dec 21, 2018
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Dec 21, 2018
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Shadan Karim
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Dec 21, 2018
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Shadan Karim
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Satbir
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Dec 21, 2018
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close this question bro
https://gateoverflow.in/118392/gate2017-2-47
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A computer uses two level cache L1 and L2 and in 2000 memory references there are 320 misses in L1 cache and 150 misses in L2lcache. If the miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time of L2 is 10 clock cycles what is the average memory access time?
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ME TEST SERIES QUESTION ON PIPELINE
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Deepanshu
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ME TEST SERIES DOUBT
A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor. P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns while the design P2 has 6pipeline stage with 3 ns each (execution time). The time that can be saved by P2 over P1 for executing 1000 Instructions is _____________ ns. iam getting answer 997 but they give 1001
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