Madeeasy Test Series

Question

Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L₂ cache to memory is 120 cycles. The hit time of L₂ cache is 50 cycles.

If there are 4 memory references per instruction, the average stall per instruction is

Answer 1

 T_{avg stall/ints}  = Miss in L1/int * Hit in L2 + Miss in L2/int * Miss Penality in L2(memory access )

here    4 memory for 1 instruction 
so for 1000 memory =  1000/4 = 250 

Miss in L1 = 150 Miss in L2 = 100 Hit time L2 = 50 Miss penalty L2 = 120 

therefore  T_{avg stall/ints}  = $\frac{150}{250}$*50 + $\frac{100}{250}$*120 = 78

Comments

So, there is no stall if a memory reference is an L1 hit?

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stalls are for misses i think.

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@Arjun sir, correct me if i am wrong

(150/250)×50 + (150/250)(100/250)×(120)

This should be the answer because memory will be accessed only when miss in L1and L2.

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why miss rate is not 100/150 here? since actually out of 150 times 100 times memory access is occuring and rest 50 times l2 cache is being accesed.

Answer 2

4 memory references → 1 instruction
1000 memory references → ? instructions.
Number of instructions = 10004=250 [#  # ]=[#  1# ×ℎ 2]+[#  2# ×  2]
=[150250×50]+[100250×120]
=[30+48]=78

Answer 3

Simplest Approach!
Just think how we can get stall,

if I went to L1 and I get a miss then to overcome it either go to L2 and rectify it or you went to L2 and you also get a miss there.

(150/250) [ 50+ (100/150)*120)= 78.