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if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns.

How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?

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In non-pipelined we dont consider the buffer delay,

so time required for 1 instruction in non pipelined system = 2+3+4+5+6=20ns

For n instructions =n*20

Time required in Pipelined system = 5*(7)+(n-1)*7=7n-28

Now, speed up = Time(non-pipelined)/Time(pipelined)

                         =20n/7n-28

For large value of n,= 20n/7n = 2.86

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