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$S_{1}$ and $S_{3}$ ?

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i am getting, all are true

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what is the single instruction latency you get in $S_{1}$ and $S_{2}$

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oh sorry, read in reverse... s2 is out

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If you say s1 as true then s3 will be true right

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s1 and s3 are true

Answer 1

1.Since n is not given...so throughput will be 1/pipeline cycle time
   which is 1/10 (M-1) and 1/7.5(M-2)...Hence M2 is always faster than M1

2.Latency is after how much time new i/p is given to system which is pipeline cycle time
     For M-1 Tp=10   and for M-2   Tp=7.5 Hence M-2 has shorter latency

3.Consider n=1  M1<M2 so not always true

Answer S1,S2 only