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Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages, (EX1 and EX2) with equal delay i.e. (8 /2) and ID stage is divided into 3 substages (ID1, ID2 and ID3) with equal delays of (6 /3). In the pipeline 'x' and 'y' memory reference instructions are not overlapped so the penalty of memory reference instructions in the pipeline 'x' is 4 cycles and in the pipeline 'y' is 8 cycles. If the program contain 20% of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y?

  1. 0.727

  1. 0.902

  1. 0.665

  1. 0.825

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pipeline-X:

no. of stages =5 [IF ID OF EX WB]

speedup$(S_X)=\frac{no. \;of \;stages}{(1+no.\;of \;stalls\; per \;instruction)} $

20% memory instruction which are not overlapped so these will create extra stalls,so no. of stalls per instruction=.20*4=.8

$S_X=\frac{5}{(1+.8)}=2.77 $

pipeline-Y:

no.of stage are increased as ID have three sub stages and EX have two sub stages ,so total no. of stages= 8

20% memory instruction which are not overlapped so these will create extra stalls,so total no. of stalls per instruction=.2*8=1.6

$S_Y=\frac{8}{(1+1.6)}=3.076 $

ratio of ($S_X \;and \;S_Y)=\frac{2.777}{3.076}=.9002$
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