0 votes 0 votes CO and Architecture co-and-architecture pipelining + – Prateek Raghuvanshi asked Dec 25, 2018 • retagged Jul 25, 2022 by Shubham Sharma 2 Prateek Raghuvanshi 427 views answer comment Share Follow See all 7 Comments See all 7 7 Comments reply Show 4 previous comments Prateek Raghuvanshi commented Dec 25, 2018 reply Follow Share @ kumar.dilip bro whole instruction size is 3 words ,only 1 word instruction will be fetched and remaining words (2) will be fetched during ID . 0 votes 0 votes Prateek Raghuvanshi commented Dec 25, 2018 reply Follow Share @ Shaik Masthan @Mk Utkarsh @aambazinga 0 votes 0 votes Psy Duck commented Sep 6, 2022 reply Follow Share If it happened @Prateek Raghuvanshi then how would CPU start decode??if the mode and addresses are in the next 2 words 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 IF IF IF IF IF IF ID ID ID ID ID ID EX EX EX WR WR IF IF ID ID EX EX WR WR IF IF IF IF IF IF ID ID ID ID ID ID EX EX EX WR WR IF IF IF IF IF IF ID ID ID ID ID ID EX EX EX WR WR Psy Duck answered Sep 6, 2022 Psy Duck comment Share Follow See all 0 reply Please log in or register to add a comment.