Given the following information:
- TLB hit rate $95$%, TLB access time is $1$ cycle.
- Cache hit rate $90$%, cache access time is $1$ cycle.
- When TLB and cache both get miss; page fault rate is $1$%.
- The TLB access and cache access are sequential.
- Access to main memory require $75$ cycles.
- Access to hard drive require $50,000$ cycles.
The average memory access latencies when the cache is physically addressed (in cycles) (up to $2$ decimal places) is__________.