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5 votes
5 votes

Given the following information:

  • TLB hit rate $95$%, TLB access time is $1$ cycle.
  • Cache hit rate $90$%, cache access time is $1$ cycle.
  • When TLB and cache both get miss; page fault rate is $1$%.
  • The TLB access and cache access are sequential.
  • Access to main memory require $75$ cycles.
  • Access to hard drive require $50,000$ cycles.

The average memory access latencies when the cache is physically addressed (in cycles) (up to $2$ decimal places) is__________.

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1 Answer

4 votes
4 votes

Average memory access time = 
TLBhit (TLB time + Cache Hit (Cache time ) + Cache Miss(Main memory time + Cache Time) )+
TLBmiss(TLB time+Main Memory Time + Cache Hit (Cache time ) +
              Cache Miss ( Cache Time + Page Fault(HDD time) + (1-Page fault)Main memory time))
Verify once!!

 

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