GATE Overflow | Mock GATE | Test 1 | Question: 61

Question

A $5$ stage pipeliine is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the Throughput (in MIPS) of the system if $20\%$ of the instrucitons are branch instructions? Ignore the overhead of buffer register. Each stage is having same amount of delay. The pipeline clock rate is $0.1 \: GHz$. Branch penalty is $4$ cycles. (Upto $2$ decimal place).

Comments

please increase the range of answer. Even i got 55.56 it is showing incorrect answer.

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@Arjun, can you please increase the range...55.54 to 55.56 would be fine...

Neeraj would have got few more marks...

Answer 1

Average instruction execution time =

=(ideal CPI + frequency of branch instructions*Branch_Penalty)*Cycle Time

Cycle Time $= 1/0.1Ghz = 10ns$

$=(1+.2*4)10 ns = 18 ns$

$18 ns = 1$ instruction, therefore

$1sec = 55.55 MIPS$

Comments

While calculating  Average instruction execution time =

=(ideal CPI + frequency of branch instructions*Branch_Penalty)*Cycle Time
 

Why we have not multiplied Ideal CPI with 0.8 (for non branch instructions)

=(0.8*1+.2∗4)10ns=16ns

 

What's wrong with this??

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@Abhishek Gupta 1

You're not using that formula correctly. When stall cycles are x, total cycles = x+1 because 1 CPI is compulsory.

So, $0.8(1)+0.2(5)=1.8$ cycles = $18ns$

 

Or, equivalently, you can do

$1+0.2(4)=1.8$ cycles = $18ns$

This equation reads that each instruction takes 1 CPI, and 0.2 instructions take 4 additional cycles.