nptel Assignment

Question

 

Comments

The answer in the assignment is not visible.

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register_user_19 explain me how t2 ,t3

how our address is going to be in memory already ??? how will know that this memory address we want...in t4 we are putting instruction in instruction register i.e why fetch.   how r u fetching without putting instruction in instruction register...

\u r doing t2 means put from memory to memory data bus then increment pointer .......there is not a bit of fetch here 

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@Deepanshu

page number 6,7:-  https://www.slideshare.net/dileepkumar342/16-control-unit
 

Answer 1

basic rule for clock cycle grouping -
page number 6,7:-  https://www.slideshare.net/dileepkumar342/16-control-unit

t2 ,t4 -> cannot be in a same cycle (read and write in the same register in a same cycle).

t2,t3 is a answer

Comments

Deepanshu,

yes, in the above comment only 3 clock cycle is use

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okk read that but i am asking theoretcial meaning of clock cycle grouping

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In the same clock cycle,2 operations are performed, when a timing signal is applied.

eg -->t3 : PC+1 -> PC ; MBR -> IR. When timing signal t3 is applied 2 operations occur in same timing signal.