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in CO and Architecture by Active (1.8k points) | 121 views
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all4 are possible see how...

first from pc we take address and give to address register

then address control bus to memory then to memory bus

and from memory bus to instruction register ..... and also increment program counter at same clock it is more efiicent

so all of above is answer
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T2 ,T3 ???
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The answer in the assignment is not visible.
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 explain me how t2 ,t3

how our address is going to be in memory already ??? how will know that this memory address we want...in t4 we are putting instruction in instruction register i.e why fetch.   how r u fetching without putting instruction in instruction register...

\u r doing t2 means put from memory to memory data bus then increment pointer .......there is not a bit of fetch here 

+1

1 Answer

+2 votes
basic rule for clock cycle grouping -
page number 6,7:-  https://www.slideshare.net/dileepkumar342/16-control-unit

t2 ,t4 -> cannot be in a same cycle (read and write in the same register in a same cycle).

t2,t3 is a answer
by Active (2.3k points)
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 okk so clock cycle grouping means that only one clock used??

+2
t1 : PC->MAR

t2: Memory -> MBR

t3 : PC+1 -> PC ; MBR -> IR

OR

t1 : PC->MAR

t2: Memory -> MBR; PC+1 -> PC

t3 : MBR -> IR
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yes, in the above comment only 3 clock cycle is use

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okk read that but i am asking theoretcial meaning of clock cycle grouping
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In the same clock cycle,2 operations are performed, when a timing signal is applied.

eg -->t3 : PC+1 -> PC ; MBR -> IR. When timing signal t3 is applied 2 operations occur in same timing signal.
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