0 votes 0 votes CO and Architecture nptel-quiz co-and-architecture + – amitqy asked Dec 31, 2018 amitqy 1.1k views answer comment Share Follow See all 5 Comments See all 5 5 Comments reply Show 2 previous comments amitqy commented Dec 31, 2018 reply Follow Share The answer in the assignment is not visible. 0 votes 0 votes Deepanshu commented Dec 31, 2018 reply Follow Share register_user_19 explain me how t2 ,t3 how our address is going to be in memory already ??? how will know that this memory address we want...in t4 we are putting instruction in instruction register i.e why fetch. how r u fetching without putting instruction in instruction register... \u r doing t2 means put from memory to memory data bus then increment pointer .......there is not a bit of fetch here 0 votes 0 votes register_user_19 commented Dec 31, 2018 reply Follow Share @Deepanshu page number 6,7:- https://www.slideshare.net/dileepkumar342/16-control-unit 1 votes 1 votes Please log in or register to add a comment.
2 votes 2 votes basic rule for clock cycle grouping - page number 6,7:- https://www.slideshare.net/dileepkumar342/16-control-unit t2 ,t4 -> cannot be in a same cycle (read and write in the same register in a same cycle). t2,t3 is a answer register_user_19 answered Dec 31, 2018 register_user_19 comment Share Follow See all 5 Comments See all 5 5 Comments reply Deepanshu commented Dec 31, 2018 reply Follow Share register_user_19 okk so clock cycle grouping means that only one clock used?? 0 votes 0 votes register_user_19 commented Dec 31, 2018 reply Follow Share t1 : PC->MAR t2: Memory -> MBR t3 : PC+1 -> PC ; MBR -> IR OR t1 : PC->MAR t2: Memory -> MBR; PC+1 -> PC t3 : MBR -> IR 2 votes 2 votes register_user_19 commented Dec 31, 2018 reply Follow Share Deepanshu, yes, in the above comment only 3 clock cycle is use 0 votes 0 votes Deepanshu commented Dec 31, 2018 reply Follow Share okk read that but i am asking theoretcial meaning of clock cycle grouping 0 votes 0 votes amitqy commented Jan 1, 2019 reply Follow Share In the same clock cycle,2 operations are performed, when a timing signal is applied. eg -->t3 : PC+1 -> PC ; MBR -> IR. When timing signal t3 is applied 2 operations occur in same timing signal. 0 votes 0 votes Please log in or register to add a comment.