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a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is

in Digital Logic by (187 points)
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i am getting 15
0
Even I am getting 15. I think the answer given in the book is wrong.
0
simply ignore their answer
0
Yaah 15 is correct

1 Answer

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CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 0 1 0
4 0 1 0 1
5 0 0 1 0
6 1 0 0 1
7 1 1 0 0
8 0 1 1 0
9 1 0 1 1
10 1 1 0 1
11 1 1 1 0
12 0 1 1 1
13 0 0 1 1
14 0 0 0 1
15 0 0 0 0

Therefore after 15 clock cycle the output will become 0000.

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