0 votes 0 votes a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is Digital Logic digital-logic shift-registers made-easy-booklet + – Jyoti Kumari97 asked Dec 31, 2018 edited Mar 5, 2019 by ajaysoni1924 Jyoti Kumari97 1.9k views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Shaik Masthan commented Dec 31, 2018 reply Follow Share i am getting 15 2 votes 2 votes Jyoti Kumari97 commented Dec 31, 2018 reply Follow Share Even I am getting 15. I think the answer given in the book is wrong. 0 votes 0 votes Shaik Masthan commented Dec 31, 2018 reply Follow Share simply ignore their answer 0 votes 0 votes Magma commented Dec 31, 2018 reply Follow Share Yaah 15 is correct 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes CLK Q3 Q2 Q1 Q0 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 0 1 0 4 0 1 0 1 5 0 0 1 0 6 1 0 0 1 7 1 1 0 0 8 0 1 1 0 9 1 0 1 1 10 1 1 0 1 11 1 1 1 0 12 0 1 1 1 13 0 0 1 1 14 0 0 0 1 15 0 0 0 0 Therefore after 15 clock cycle the output will become 0000. noob_coder answered Mar 8, 2019 noob_coder comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes Yes, 15 is the correct answer. Abhrajyoti00 answered Jun 5, 2021 Abhrajyoti00 comment Share Follow See all 0 reply Please log in or register to add a comment.