Made Easy Test Series

Question

Assertion(A): The DMA technique is more efficient than the interrupt-driven technique for high volume I/O data transfer.

Reason(R): The DMA technique doesnt make use of the interrupt mechanism.

(a) Both A and R are true and R is the correct explanation of A.

(b) Both A and R are true but R is not the correct explanation of A.

© A is true but R is false.

(d) A is false but R is true.

Comments

I too think C as correct answer.

In DMA we use interrupts to ask CPU permission to access bus.(bus request)

Correct me if I'm wrong

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I think, to access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA.

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dma generates an interrupt after the operation of data count register completes then dmac simply sends the interrupt single to cpu then cpu checks the status io that any ip request is pending or not

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So what's the answer now? A or C?

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A should be the answer as DMA is more efficient for bulk transfer because it does not use interrupt driven mechanism.

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But counting whether the transferring of data is done by data register is part of dmac which sends interrupt to the CPU hence ans will be C na ?

Correct me if I am wrong

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@Shobhit Joshi  If Data Count is zero, then DMA controller interrupts CPU and CPU will check the status of DMA.

we are using the interrupt mechanism here but yes its not complete Interrupt mechanism.

So saying "DMA technique does not make use of the interrupt mechanism" is partially correct because I/O is not interrupt here 

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@Hemanth_13 interrupt mechanism and making use of interrupts are two different things. 

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I think whenever there is an interrupt, the same process of calling the ISR and execution of it is done right???

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@Hemanth_13 When at the end of transfer of data the DMA needs to release the bus it would use bus release signal and the CPU would acknowledge it, I don't think DMA will use ISR

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Whenever DC is zero then how will the CPU know it can take back and reuse the bus, I think it will be done by an interrupt signal from DMA controller to CPU

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C?

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hmm i m withGupta731

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Even I marked it as C..But made easy gave the solution as A

They gave the reason as:

The DMA technique doesnt make use of interrupt mechanism that's why it is more efficient than the interrupt driven technique for high volume I/O data transfer.

But I dont think this reasoning is right because DMA still uses interrupt mechanism..the thing that makes DMA efficient is that the CPU isnt involved for transferring data to and from the I/O device and memory. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.

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hmm u r right

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Yes exactly that why I think the answer should be C.

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yeah...i marked the same wih same reasoning.

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https://gateoverflow.in/279077/dma-and-interrupt-mechanism

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Gurdeep Saini

whats the final conclusion?Is the answer A or C?

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all of you are discussing C but in this link https://www.aspirebuzz.com/content/s1the-dma-technique-more-efficient   they told A and also explaining but i did not reach to any conclusion until now .

if you got after reading given link. then reply .....

@Gupta731 this a typed question ,remove flag from here and add this flag to this https://gateoverflow.in/279077/dma-and-interrupt-mechanism

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@Gurdeep Saini 

"Disabled" and " Not used" after different terms right ? 

( "Disabled" is as per ur provided link )

Anyways, question seems ambiguous.