2 votes 2 votes The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is 0.25 0.5 1 2 Digital Logic gate2013-dl-ee flip-flop digital-logic + – Sambhrant Maurya asked Jan 4, 2019 Sambhrant Maurya 3.9k views answer comment Share Follow See all 9 Comments See all 9 9 Comments reply Show 6 previous comments Shamim Ahmed commented Jan 4, 2019 reply Follow Share Its mod 2 counter. So its diving the clock frequency by 2 right ? 0 votes 0 votes Abhisek Tiwari 4 commented Jan 4, 2019 reply Follow Share @Shamim Ahmed yes 0 votes 0 votes as8297 commented Sep 17, 2019 reply Follow Share Image of Time Cycle Graph I hope this can explain you the solution more easily. 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes From the given circuit ,X=1, so T toggles for every negative edge. if you draw the waveform , clock will get doubled. so frequencey will gets reduce to half. therefore the answer for this problem becomes 0.5KHz, varunraj answered Apr 2, 2020 varunraj comment Share Follow See all 0 reply Please log in or register to add a comment.