search
Log In
0 votes
789 views

The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The frequency of the signal available at Q is?

 

  1. 5 Khz
  2. 10 Khz
  3. 1 Khz
  4. 0.5 Khz
in Digital Logic 789 views
0
5 Khz

2 Answers

1 vote
 
Best answer

Answer : 5 Khz

 


selected by
0 votes

 

Here Time Period of Signal at Q will get Doubled, hence frequency is halved. See my solution below.

Solution

 

Related questions

0 votes
1 answer
1
0 votes
0 answers
2
601 views
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
asked Jan 5, 2019 in Digital Logic Sambhrant Maurya 601 views
0 votes
1 answer
4
647 views
The following sequential circuit has initial state $QAQB = 00$ with one input $X$ and one output $Z.$ What is the minimum input sequence which takes the machine to state $11?$ $(A) 00$ $(B) 10$ $(C) 11$ $(D)$ State $11$ is not reachable
asked Feb 7, 2017 in Digital Logic Samujjal Das 647 views
...