Digital Logic madeeasy

Question

A 4 bit right shift register is shifting the data to the right for every clock pulse. The serial input D is derived by using XOR gates as shown. After 3 clock pulses the content in the register is to be 1010 at Q0Q1Q2Q3. What were the initial contents of the register?

• A. 1100
• B. 1010
• C. 0011
• D. 0101
  I’m getting the answer as 0101 but it’s given 0011

Comments

It cannot be 0101...

0101--> 1011-->0111--> 1110

0011--> 0110-->1101-> 1010

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you did  left shifting i think so

Answer 1

INPUT(q3⊕q2⊕q0)	Q3	Q2	Q1	Q0
-	0	0	1	1
1	1	0	0	1
0	0	1	0	0
1	1	0	1	0

Comments

The order is Q0Q1Q2Q3 please check it