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Self Doubt

manisha11 asked in CO and Architecture Jan 5, 2019 retagged Jul 23, 2022 by Shubham Sharma 2

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What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?

co-and-architecture
cache-memory
direct-mapping

manisha11 asked in CO and Architecture Jan 5, 2019 retagged Jul 23, 2022 by Shubham Sharma 2

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S Ram asked in CO and Architecture Jan 12, 2019

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Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

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AnilGoudar asked in CO and Architecture Oct 19, 2017

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The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory words May respond to this Physical Address? Block size is P words.

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lalitver10 asked in CO and Architecture Aug 19, 2022

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Satbir asked in CO and Architecture Jan 13, 2020

3,835 views

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How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

3.8k views

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normal

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