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Self Doubt

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What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?

co-and-architecture

asked Jan 5, 2019 in CO and Architecture by manisha11 Active (2.3k points) | 16 views

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Related questions

+2 votes

1 answer

1

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked May 23, 2019 in CO and Architecture by Hirak Active (3.6k points) | 102 views

co-and-architecture
pipelining
haza

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0 answers

2

Self doubt
please arrange them in increasing order of speed: Relative addressing , Absolute addressing , Register addressing , Register Indirect addressing , Indirect addressing , Base addressing , indexed addressing

asked Jan 27, 2019 in CO and Architecture by iamdeepakji (155 points) | 42 views

co-and-architecture

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0 answers

3

Self Doubt
GATE2018-50 https://gateoverflow.in/204125/gate2018-50 Why can't I do this question with $(k+(n-1))*t_p$ For PO stage: $0.40*3 + 0.35*2 + 0.25*1 = 2.15$ cycles. This is larger than all the 5 stages of the given pipeline. So applying the above formula it gives $(5+99)*2.15 =224$ cycles. why we use the expanded form of the same formula $k*t_p+(n-1)t_p$ and get answer as $219$ cycles

asked Jan 13, 2019 in CO and Architecture by Gupta731 Active (4.8k points) | 42 views

co-and-architecture

0 votes

0 answers

4

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

asked Jan 12, 2019 in CO and Architecture by S Ram Active (1.7k points) | 49 views

cache-memory
direct-mapping
co-and-architecture

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