0 votes 0 votes CO and Architecture co-and-architecture made-easy-test-series cache-memory + – jatin khachane 1 asked Jan 7, 2019 edited Mar 4, 2019 by Rishi yadav jatin khachane 1 517 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply jatin khachane 1 commented Jan 7, 2019 reply Follow Share In solution they have considered Miss ratio for L2 ==> 150 / 2000 But considering hierarchical structure ..it should be 150 / 320 ?? 0 votes 0 votes Shaik Masthan commented Jan 7, 2019 reply Follow Share yes... I don't know why you post screenshot, is there any cause behind it ? 0 votes 0 votes jatin khachane 1 commented Jan 7, 2019 reply Follow Share ..it takes time for typing and if wrong values typed whole discussion will get wrong .. Sorry i will edit all such posts 👍 1 votes 1 votes Shaik Masthan commented Jan 7, 2019 reply Follow Share if you edit your posts after discussion, then there is no problem, if you left them that lead to problem 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes 26 clock cycles mohd. ashfaq answered Jan 7, 2019 mohd. ashfaq comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes L1 miss rate = 320/2000 L2 miss rate = 150/320 so EMAT = $1+ 320/2000(10 + 150/320(300))$ = 25.1 clock cycle smsubham answered Mar 23, 2020 smsubham comment Share Follow See all 0 reply Please log in or register to add a comment.