in CO and Architecture
1 vote
1 vote

I was going through this problem:


Consider a disk drive with the following specifications:

16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:

  1. 10
  2. 25
  3. 40
  4. 50

The solution given was:

$512 KB-1/50  sec $

4 Byte transfer will take total :$4/(512×50×2^{10})=152.58 ns$

DMA will transfer 4B in 40nsec 

So, Cpu will be blocked $(40/152.58)=26%$ of time 

Best matching answer is (B).


Why we are not considering the fact that whenever 1 byte word is ready, it is sent to memory? Disk buffer is of 1B. Thus, we cannot accumulate 4B data in disk buffer and send it in one go. Also, we cannot do things in parallel. That is once disk buffer gets 1B data, it is output on system bus, then next byte and so on for 4 bytes. So, we need to send 1B at a time, even though bus width is 4B. So full 4B bandwidth of bus is never utilised and hence we need 4 cycles of 40 ns each, instead of 1 cycle of 40 ns. All this time system bus need to be reserved / stolen by DMA from processor. If disk buffer D would have larger than system bus S, we would have sent S bytes as soon as received and then next S bytes and so on, till all D bytes are sent. So parallelization can be done when disk buffer is bigger than bus width, but not when bus width is bigger than disk buffer. Or is it like there is some intermediate buffer wherein we empty the disk buffer. And only after 4B are there in intermediate buffer, we send it over system bus.

in CO and Architecture

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