A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.?
@Shaik Masthan Could you please help!
some data missing in the question ( Howmany memory references each instruction takes ? )
still you have problem, then comment !
@Shaik Masthan Thanks :)