GATE 2019 2-way set associative

Vikas123 asked Jan 7, 2019

342 views

0 votes

plz explain …..??

Operating System
cache-memory
co-and-architecture

+ –

Vikas123 asked Jan 7, 2019

Vikas123

342 views

See all

2 2 Comments

Vikas123

commented Jan 7, 2019

but answer is given 2

0 votes

Himanshu Kumar Gupta

commented Sep 8, 2020

yes 2 is correct answer

0 votes

Please log in or register to add a comment.

Please log in or register to answer this question.

0 Answers

Voting & Accepting an answer helps improve the community

← Previous Next →

← Previous in category Next in category →

Related questions

3 votes

1 answer

Shubhanshu asked Aug 5, 2017

1,039 views

CO: Working of multiplexer, comparator and encoder in 2-way set associative mapping
Draw the diagram which shows the mechanism of fetching the data in 2-way set associative mapping using multiplexer, comparator, and encoder?

Draw the diagram which shows the mechanism of fetching the data in 2-way set associative mapping using multiplexer, comparator, and encoder?

Shubhanshu

1.0k views

Shubhanshu asked Aug 5, 2017

CO and Architecture
co-and-architecture
cache-memory
multiplexer

+ –

2 votes

2 answers

Na462 asked Nov 14, 2018

637 views

Set way Associative

Na462

637 views

Na462 asked Nov 14, 2018

CO and Architecture
co-and-architecture
cache-memory
numerical-answers

+ –

3 votes

3 answers

Shubhanshu asked Nov 6, 2017

3,149 views

Hardware requirement in 16-way Set Associative Cache
Cache size 32 KB Block size = 32 Bytes Address size = 28 bit. Associativity of Cache = 16 Determine what is the hardware requirement to design the 16-way set associative cache. Hardware requirement -> Mux, Comparator, Demux, Decoder, Encoder ... lines are 5. 4) 64 And gates 5) 1 OR gate input line = 64 Someone, please verify these attributes??

Cache size 32 KBBlock size = 32 BytesAddress size = 28 bit.Associativity of Cache = 16Determine what is the hardware requirement to design the 16-way set associative cach...

Shubhanshu

3.1k views

Shubhanshu asked Nov 6, 2017

CO and Architecture
cache-memory
co-and-architecture
multiplexer
memory-interfacing

+ –

4 votes

1 answer

focus _GATE asked Jun 7, 2015

14,088 views

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache.
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing ... used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block dia...

focus _GATE

14.1k views

focus _GATE asked Jun 7, 2015

CO and Architecture
co-and-architecture
cache-memory

+ –

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

2 2 Comments reply

Please log in or register to add a comment.

Please log in or register to answer this question.

0 Answers

Related questions

2 2 Comments