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+32 votes

Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays $\delta_1 = 2 ns$ and $\delta_2 = 4 ns$ as shown in the figure. Both XOR gates and all wires have zero delays. Assume that all gate inputs, outputs, and wires are stable at logic level $0$ at time $0$. If the following waveform is applied at input $A$, how many transition(s) (change of logic levels) occur(s) at $B$ during the interval from $0$ to $10$ ns?

  1. $1$
  2. $2$
  3. $3$
  4. $4$
in Digital Logic by Active (3.5k points)
edited by | 5.8k views

Option D is correct

@bikram sir , I have following doubt on best answer .

1. This status will same for two seconds more. So, at 5th sec o/p of second non-inverting buffer reach at i/p of second xor gate because of its delay of 4sec i.e 1.

5th sec                                 1xor1=0                                                  0xor1=1

6 Answers

+81 votes
Best answer


Let us plot the logic states at the various points of interests in this circuit.



Note that,   is not an inverter but a buffer used for introducing delay.

∴ Output at 'P' and 'R' will be obtained at $2$ ns and $4$ ns respectively after the change in their inputs.

Hence, waveforms of 'P' and 'R' are shifted by $2$ ns and $4$ ns as compared to their inputs.

Also, note that 'Q' and 'B' are plotted using their corresponding input waveforms.

Finally, we can see that there are $4$ changes in logic levels in the waveforms of 'B'.

Answer is : Option D

by Active (1.5k points)
edited by
Best explanation :)
This should be best answer:)
@rahul sharma 5 I have doubt at R up down . Can you explain it ?
@hem Chandra... Basically  2 inputs to the xor2 gate.

Q and  Q(delayed by 4 clocks)

You can see in the answer figure that input of the xor2 is Q and R. Now according to xor rules the resulting clock is produced.
Why is R going down at 7th sec?
b/c Q is up for 2 clock only
Okay i got it. While Q's transition from 0 to 1 at 1th sec is propagated through 2nd buffer and the effect is felt at 5th sec(in R), similarly the effect of Q's transition from 1 to 0 at 3th sec will be reflected at R after 4 secs from 3th sec i.e. at 7th sec. So R goes up at  5th sec(1th sec +4 secs delay) and goes down from 1 to 0 at 7th sec(3th sec +4 secs delay).

Am i right? Correct me if needed. Thank you.
These timing diagram questions have always haunted me but that was wonderfully explained!

I used to think these questions are really tough but your explanation made it look simple and feasible to understand. Thanks.
Can someone tell why R at 7th sec goes to 0. I think it should remain1 for whole cycle.

Anu007 can you please elaborate it ?

Thank you so much.
why first buffer is active after $3$ ns??

It is given in question , that it's delay is $2$ ns.

So, it should be active after $2$ ns.

isnot it??


first buffer produces 0 @2ns because input signal(i.e A) @0ns is 0 itself.

First buffer will produce 1, only 2ns after input signal is 1.

+17 votes

Here notice that first delay is 2nS while secong delay in 4nS. A non-inverting buffer with delay δ means, whatever is the input of the buffer that will be output after time δ.

In the first interval A1 becomes one but A2 will become one after 2ns as there is a delay of 2ns.

Interval A A1 A2 O B1 B2 B
0 0 0 0 0 0 0 0
1 1 1 0 1 1 0 1
2 1 1 0 1 1 0 1
3 1 1 1 0 0 0 0
4 1 1 1 0 0 0 0
5 1 1 1 0 0 1 1
6 1 1 1 0 0 1 1
7 1 1 1 0 0 0 0
8 1 1 1 0 0 0 0
9 1 1 1 0 0 0 0
10 1 1 1 0 0 0 0

Hence, we have 4 transitions. The are in 1st, 3rd, 5th and 7th interval.

Answer Source

by Active (4.1k points)
edited by
Understand the logic from given table very nice. thank you for posting this here.
why does B2 becomes 1 at t=5?
+8 votes

So, option D is correct.

by Active (2.4k points)
nice answer ...

i have one doubt tht at t=5 second how at second xor will b 1 ?(means it will not change to 0)
+6 votes

Let output first xor gate is P .

on completion of:-               o/p of P                                               o/p of B
0th sec                                    0                                                       0

1st sec                                   1xor0=1                                              1xor0=1

This status will same for two seconds.After o/p of first non-inverting buffer reach at i/p of first xor gate then,

3rd sec                                   1xor1=0                                               0xor0=0

This status will same for two seconds more. So, at 5th sec o/p of second non-inverting buffer reach at i/p of second xor gate because of its delay of 4sec i.e 1.

5th sec                                 1xor1=0                                                  0xor1=1

At 7th sec  o/p of p which was changed at 3rd sec reach at i/p second xor gate.

7th sec                                 1xor1=0                                                     0xor0=0

Now this status same for 3 seconds more. So total 4 logic level changes at 1st,3rd,5th and 7th sec.
So option is d

by Active (3.2k points)
Why in 3rd second output of B XOR gate is 1? I think it should be 0 as the input without buffer will become 0(output of XOR A) and the second input with buffer is already 0 because delay time has not exceeded so how can its result is 1. Please explain
That's my mistake. I've corrected :)
Can you explain in detail why at 5th second why the B gate will output 1?

I didnt understand output at 7th second. Why  o/p of p which was changed at 3rd sec reach at i/p second xor gate ?


Assume Output of First XOR gate (G1) = Y

Output of First buffer is = X ( buffer delay = 2ns)

Output of 2nd buffer = Z ( buffer delay = 4ns)

Final Output is = F

XOR gates Gand G2 are not having any delay, so they respond immediately. 

@debashish deka
tell me one thing in Z(4 ns delay) after the high why it goes to low ?
I hope you noticed Y signal going down.
ur hope is right but still not getting what u want to say.
its k y has 4 ns delay but why after that 6 clock cycle why it going down .


Chk this diagram, hope doubt will be clear

Though XOR is active all the time, one side of XOR always be $0,$ until the delay period completed.  and the signal started at time $1,$ not at $0.$
+1 vote
ans will be D

A  0000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

A' 0000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111(2 sec delay)


A'''0000000000000000000000000000000000000000000000000000000000001111111111111111111100000000000000000(4 sec delay)


B is final out put where 4 changes in logic

so ans is 4
by Active (4k points)
+1 vote

hope you can understand,

by (39 points)

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