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Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays $\delta_1 = 2 ns$ and $\delta_2 = 4 ns$ as shown in the figure. Both XOR gates and all wires have zero delays. Assume that all gate inputs, outputs, and wires are stable at logic level $0$ at time $0$. If the following waveform is applied at input $A$, how many transition(s) (change of logic levels) occur(s) at $B$ during the interval from $0$ to $10$ ns?

  1. $1$
  2. $2$
  3. $3$
  4. $4$
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6 Answers

Best answer
132 votes
132 votes

 

Let us plot the logic states at the various points of interests in this circuit.

 

$\underline{\text{Explanation}:}$

Note that,   is not an inverter but a buffer used for introducing delay.

∴ Output at 'P' and 'R' will be obtained at $2$ ns and $4$ ns respectively after the change in their inputs.

Hence, waveforms of 'P' and 'R' are shifted by $2$ ns and $4$ ns as compared to their inputs.

Also, note that 'Q' and 'B' are plotted using their corresponding input waveforms.

Finally, we can see that there are $4$ changes in logic levels in the waveforms of 'B'.

Answer is : Option D

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25 votes
25 votes

Here notice that first delay is 2nS while secong delay in 4nS. A non-inverting buffer with delay δ means, whatever is the input of the buffer that will be output after time δ.

In the first interval A1 becomes one but A2 will become one after 2ns as there is a delay of 2ns.

Interval A A1 A2 O B1 B2 B
0 0 0 0 0 0 0 0
1 1 1 0 1 1 0 1
2 1 1 0 1 1 0 1
3 1 1 1 0 0 0 0
4 1 1 1 0 0 0 0
5 1 1 1 0 0 1 1
6 1 1 1 0 0 1 1
7 1 1 1 0 0 0 0
8 1 1 1 0 0 0 0
9 1 1 1 0 0 0 0
10 1 1 1 0 0 0 0

Hence, we have 4 transitions. The are in 1st, 3rd, 5th and 7th interval.

Answer Source http://www.techtud.com/example/gate-2009-xor-gate-non-inverting-buffer

11 votes
11 votes

So, option D is correct.

6 votes
6 votes

Let output first xor gate is P .

on completion of:-               o/p of P                                               o/p of B
0th sec                                    0                                                       0

1st sec                                   1xor0=1                                              1xor0=1

This status will same for two seconds.After o/p of first non-inverting buffer reach at i/p of first xor gate then,

3rd sec                                   1xor1=0                                               0xor0=0

This status will same for two seconds more. So, at 5th sec o/p of second non-inverting buffer reach at i/p of second xor gate because of its delay of 4sec i.e 1.

5th sec                                 1xor1=0                                                  0xor1=1

At 7th sec  o/p of p which was changed at 3rd sec reach at i/p second xor gate.

7th sec                                 1xor1=0                                                     0xor0=0
 

Now this status same for 3 seconds more. So total 4 logic level changes at 1st,3rd,5th and 7th sec.
So option is d

Answer:

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