3 votes 3 votes in this question as said block size contains two 32 bit word, and byte addressable, so each time fetching a block from main mem will fetch 8 byte, so my doubt is, BCD address 200 and 204 in decimal 512 and 516, fetching block at address 200 also contains bytes at address 204 so for 200 miss and 204 will next time, bcz 204 already fetched during fetching of 200 yes asked Dec 2, 2015 • edited Dec 2, 2015 by yes yes 747 views answer comment Share Follow See all 3 Comments See all 3 3 Comments reply yes commented Dec 2, 2015 reply Follow Share for clearity 0 votes 0 votes Arjun commented Dec 30, 2015 reply Follow Share Why you used BCD? Its not mentioned in question. Also, the solution seems to assume the given addresses as block address and not memory address. 0 votes 0 votes shivanisrivarshini commented Jan 26, 2016 reply Follow Share If this is the way to solvethen why to have all those information it is just simply an LRU na 0 votes 0 votes Please log in or register to add a comment.
2 votes 2 votes Cache contain 8 - 32bit word =8*4B= 32 B Each block consists of 32 bit word= 4 B No of block in cache = 32/4= 8 It is 2 way set associative No of sets will be 8/2 =4 Hit ratio will be 2/11 =0.18 srestha answered Dec 3, 2015 srestha comment Share Follow See all 0 reply Please log in or register to add a comment.