MadeEasy Test Series: CO & Architecture - Cache Memory

Question

A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache is increased from one word to four words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is  (Upto 2 decimal places)

Comments

Cache access time is not given, so considering it negligible. 8 cycles / word fetch from MM. 1 cycle for sending an address to MM.

Miss rate old = 14.8% , Line size = 1word

Total cycles = (0.148)*(1 * 8 + 1) = 1.332 cycles

Miss rate new = 2.6% , Line size = 4words

Total cycles = (0.026)*(4 * 8 + 1) = 0.858 cycles

Speedup = told/tnew = 1.55

Is it right answer ? 

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No. While calculating the new miss rate , they have done it this way:

total cycles= (0.026)*((8+1)*4)

idk, why we need to send the adddress to the manin memory 4 times.

Answer 1

Check the below ScreenShot ……..