1 votes 1 votes CO and Architecture made-easy-test-series co-and-architecture cache-memory + – Shubham Kumar Gupta asked Jan 10, 2019 edited Mar 3, 2019 by Rishi yadav Shubham Kumar Gupta 596 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply prashant jha 1 commented Jan 10, 2019 reply Follow Share Is it 3.6? 0 votes 0 votes Shubham Kumar Gupta commented Jan 10, 2019 reply Follow Share Yes. Can you explain? 0 votes 0 votes prashant jha 1 commented Jan 10, 2019 reply Follow Share Out of 1000 memory accesses , 40 are miss in L1 cache . And out of those 40 , 10 misses happens in L2 cache. So AMAT = 1 clock cycle + 40/1000[15 + 10/40 x 200] = 1+ 0.04x15 + 0.04 x 0.25 x 200 = 3.6 clock cycles 1 votes 1 votes Shubham Kumar Gupta commented Jan 10, 2019 reply Follow Share how you got this formula? 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes AMAT = h1*t1 + (1-h1)*h2*(t1+t2) + (1-h1)(1-h2)*(t1+t2+t3) =>$\frac{960}{1000}*1 + \frac{40}{1000}*\frac{30}{40}*(1+15) + \frac{40}{1000}*\frac{10}{40}*(1+15+200)$ =>3.6 clock cycles Rishabh Agrawal answered Jan 10, 2019 Rishabh Agrawal comment Share Follow See all 2 Comments See all 2 2 Comments reply Shubhgupta commented Jan 10, 2019 reply Follow Share just a suggestion, use simplified formula it will take less time- $T1+(1-H1)T2+(1-H1)(1-H2)T3$ 3 votes 3 votes Rishabh Agrawal commented Jan 10, 2019 reply Follow Share Thanks for this. 0 votes 0 votes Please log in or register to add a comment.