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A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor.

P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns while the design P2 has 6pipeline stage with 3 ns each (execution time).

The time that can be saved by P2 over P1 for executing 1000 Instructions is _____________ ns.

 iam getting answer 997 but they give 1001
asked in CO and Architecture by Loyal (7.7k points) | 32 views
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Answer $1001$ is right!.
0

how 

for p1 it has 16 +999*4=4012

for p2 18 +999*3=3015 difference is 997

0
how?
+1

for p1 it has 16 +999*4=4012??

here it will be  5( First instruction will take five stages, here CPI = 5)*4 + 999*4. = 4016.

0
ohhhhhhhhhh   got it

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