Any page fault would require exceptional handling as you are trying to access memory which is not present in main memory. Page Fault it self is an exception!
When you ask specifically asked for TLB, its processor architecture dependent and OS service responsible for memory translation would have very less control over it, But generally in case of software-loaded TLB (TLB with some programed controller) TLB miss would defiantly raise TLB miss exception. (in case of MIPS architecture).
To keep in mind —
#1. Exception of TLB is architecture dependent — if its just hardwared TLB, memory translator would go one translating address without raising any exceptions for kernel!
This is my understanding let me know if I missed something.
