0 votes 0 votes CO and Architecture co-and-architecture addressing-modes + – Chaitrasj asked Jan 14, 2019 retagged Jul 22, 2022 by Shubham Sharma 2 Chaitrasj 609 views answer comment Share Follow See all 10 Comments See all 10 10 Comments reply Chaitrasj commented Jan 14, 2019 reply Follow Share Answer is given as 4. My doubt is why don't we consider the memory reference needed to fetch the instruction. In question it's mentioned memory references for instruction cycle so it should include fetch decode execute all 3 right? Please help me where I am going wrong. 1 votes 1 votes aambazinga commented Jan 14, 2019 reply Follow Share number of memory references required to access the data. that's why fetch cycle not considered. 0 votes 0 votes Chaitrasj commented Jan 14, 2019 reply Follow Share @aambazinga if they had not mentioned anything about the data, nd just memory references required for instruction cycle is asked, we would include the fetch reference also right? And in this question to fetch 1 instruction, how many memory reference would be needed, 1 or 4? 0 votes 0 votes Chaitrasj commented Jan 15, 2019 reply Follow Share @Shaik Masthan can you please provide your input here.. And if we need to count the number of of memory references needed for fetching the instructions, how many it would be? 0 votes 0 votes arya_stark commented Jan 15, 2019 reply Follow Share sir :: https://gateoverflow.in/blog/5823/screenshot?show=5876 0 votes 0 votes Chaitrasj commented Jan 15, 2019 reply Follow Share Madam, I'm not sir :) Point noted. Thanks! 0 votes 0 votes Satbir commented Jan 15, 2019 reply Follow Share correct me if i am wrong. A3 <- A1 + A2. we put data in A1 and then in A2. -> 2 then we store the result(data) in A3. -> 1 Then we store address of A3.(indirect AM) ->1 so when we have to access the data of instruction cycle we can go in reverse order. -> 4 0 votes 0 votes Shaik Masthan commented Jan 15, 2019 reply Follow Share given that it is 16bit CPU ==> 16 bits at a time access. Memory = 64K word = 16 bits required ===> one memory access can be sufficient to know the value in direct mode Indirect means, it requires 2 Memory references. Instruction size = 64 bits ===> 4 memory references required So, memory references = Indirect + Direct + Direct = 2+1+1 = 4 ( without fetch ) memory references = Fetch + Indirect + Direct + Direct = 4+2+1+1 = 8 ( with fetch ) as per me, data means references of variables but not the code (i.e., not count the accessing instructions ) 0 votes 0 votes aambazinga commented Jan 15, 2019 reply Follow Share @Chaitrasj 4 memory references for whole instruction to fetch.. complete explanation is already provided by Shaik sir. 0 votes 0 votes Chaitrasj commented Jan 15, 2019 reply Follow Share Thanks @Shaik Masthan and @aambazinga and @Satbir 0 votes 0 votes Please log in or register to add a comment.