Asynchronous counter (Applied course mock 3)

Question

1. MOD-8 synchronous down counter

2. MOD-8 asynchronous up counter

3. MOD-10 asynchronous up counter

4. MOD-8 asynchronous down counter

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Please explain why it is down counter?

Comments

If we take initial state of all FF to be 0

During the first positive edge of clock, Q0 will become 1, and since Q0 is acting as clock for second FF, this transition of Q0 from 0 to 1 will act as the positive edge for 2nd FF, hence Q1 will become 1, similarly, Q2 will become 1.

So after 000 we get 111, and if we continue it we will get 011 and so on, hence I think it must be a down counter.

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Chaitrasj let's say initially $Q_0 Q_1 Q_2$ are 000

after first clock cycle $Q_0$ will be 1, remaining to FF will not change 

after second clock cycle $Q_0$ will be 0, $Q_1$ will toggle and $Q_2$ will remain unchanged

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MOD-8 asynchronous down counter ??

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Nature of clock	Position of clock feedback	Nature of Counting.
-ve ( negative)	True ( +ve O/P)	UP
+ve	False ( -ve  O/P)	Up
+ve	True ( +ve O/p)	Down
-ve	False ( -ve O/P)	Down.

Note:- 1.Opposite sign of clock and position of feedback clock is UP counter.

2. Same sign of clock and position of feedback clock id Down counter.

What is the position of clock feedback ???

If we see in above diagram clock is positive edge triggered and Q0 and 'Q0 is called feedback position.

Here clock is positive + output of first clock is coming from Q0 ( positive )  ===> same sign.

So, Down counter. 

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@Mk Utkarsh the 2nd FF will toggle only when it's clock input sees a transition from 0 to 1, since it's a positive edge triggered FF, isn't it? Then at 2nd clock, Q0 will go from 1->0, why at that instant, second FF will toggle?

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It is clearly MOD-8 Asynchronous Down Counter.

The flip-flops will toggle only when there is a positive edge in clock of previous flip-flop, else they will latch.

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thanks guys

i solved the question assuming negative edge triggering