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AppliedAi MOCK1
jatin khachane 1
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CO and Architecture
Jan 15, 2019
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Shubham Sharma 2
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An I/O device transfers a data 10MB/s over a bus which is capable of sending the data at a rate 100MB/s. Consider a processor operates at 200MHZ, and it takes 100 clock cycles to handle each DMA request. Suppose 8KB blocks of data has been transferred between I/O and main memory then calculate fraction of CPU time handling of the data transfer with DMA?
co-and-architecture
dma
jatin khachane 1
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Jan 15, 2019
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Shubham Sharma 2
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Shobhit Joshi
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Jan 15, 2019
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$0.0609 \,\%\,?$
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jatin khachane 1
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Jan 16, 2019
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did you used that x/x+y formular ?
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Shobhit Joshi
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Jan 16, 2019
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I think, the transfer is in burst mode, so the CPU is idle while the DMA transfers and active only for 100 clock cycles, so $\frac{x}{x+y}$, should be used.
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Jay Bhutada 1
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Jan 25, 2019
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@Shobhit Joshi
what is the significance of these 2 different data rates ..10MBps and 100 MBps..?
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I/O Modes | Process State Transition | COA & OS
MSQ A ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes? Synchronous I/O Asynchronous I/O Interrupt Driven I/O DMA
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Chaitanya Kale
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Sep 24, 2022
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DMA
The below question is from Made Easy Test series The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 1 2 3 0 Here answer ... My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once. Is this correct?
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Arjun
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Feb 15, 2022
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GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer
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