Consider a pipelined processor, which has $5$ stages Fetch, Decode, Execute, memory and Write back with latencies $300 \: ms$, $400 \: ms$, $350 \: ms$, $550 \: ms$ and $100 \: ms$ respectively. What is the latency of an instruction? (Assume each pipeline cost $20 \:ms$ extra for registers between the stages).
- $1700 \: ms$
- $1720 \: ms$
- $2750 \: ms$
- $2850 \: ms$