Applied Course | Mock GATE | Test 1 | Question: 61

Question

Consider a pipelined processor, which  has $5$ stages Fetch, Decode, Execute, memory and Write back with latencies $300 \: ms$, $400 \: ms$, $350 \: ms$, $550 \: ms$ and $100 \: ms$ respectively. What is the latency of an instruction? (Assume each pipeline cost $20 \:ms$ extra for registers between the stages).

• A. $1700 \: ms$
• B. $1720 \: ms$
• C. $2750 \: ms$
• D. $2850 \: ms$

Answer 1

Pipelining reduces the cycle time to the length of the longest stage plus the register delay. Latency becomes (Cycle time*N) where N is the number of stages as one instruction will need to go through each of the stages and each stage takes one cycle.
Cycle time $=550+20=570 \: ms$
Latency $=5*570 = 2850 \: ms$