A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is increased from one word to four words,the speed up of processor is achieved after increasing the line size is
doubt :
in new cache
when a fault is there
1cc for address + 8*4[word] will be required bz , the complete line got transfer when request of one word is made
in ans key it is 4*(1+8) mentioned