consider a 2-level $L_1$ and $L_2$ memory hierarchy system.The associativity of $L_1$ towards processor is more .$L_1$(cache ) has accessing time of 15 ns and $L_2$ (main memory) has an accessing time of 100 ns .writing takes 30 ns for $L_1$ and 150 ns for $L_2$.assume 30% read misses in $L_1$ memory .50% of the program instructions are read only instructions .what is the average access time for the system if it uses write through protocol?
answer given-95.25 ns
my attempt-
since here nothing is mention about hit ratio or miss ratio for write means writing is done simultaneously
so $T_w=150 ns$
$T_r=.7*15ns+.3*(100ns+15ns)=45ns$
$T_{avg}=.5*45+.5*150=97.5ns$
please verify it.
