1 votes 1 votes closed as a duplicate of: GATE CSE 2015 Set 1 | Question: 38 In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved. CO and Architecture pipelining speedup co-and-architecture + – Nandkishor3939 asked Jan 19, 2019 • closed Jan 19, 2019 by Mk Utkarsh Nandkishor3939 777 views comment Share Follow See all 0 reply Please log in or register to add a comment.