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Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?
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Instruction size = 16 bits

Address size = 128 word =7 bits

Total Two address instruction = 16 - (7 + 7) bits = 2 bits = 4

But we use only 2 two address instruction.

Remaining 2 can be used for 1 address instruction and also 7 bits by reducing an address field.

Total 1 address instruction = 2 * 2$^{7}$ = 256

But we use 100 one address instruction.

Remaining 156 along with 7 bits by reducing an address field can be used for zero address instruction.

So Total zero address instruction = 156 * 2$^{7}$ = 19968

by Junior (991 points)

Given..

16 bit instruction.

16 bit Instruction placed in 128 word memory.

..it means memory is word addressable and we have totally 128 memory references/ addresses

Total number of bits to access memory reference = log2(128) = 7 bits (1 memory reference/address size)

<-------- 16 bits ---------->

opcode + 7 bits + 7 bits = 16 bits

opcode bits =  16 - 14 = 2 bits

total 2 address instructions possible = 2 ^ 2 = 4

but, already given 2, so remaining ones = 4 -2 = 2

9 bits |  7 bits |

2  remaining  in 2 address instructions with 2 bits * with remaining 7 bits by reducing the address field

Number of 1 address instructions possible =  2 * (2 ^ 7) = 256

but, already given 100 so remaining ones = 256 - 100 = 156

for , 0 - address instruction

| opcode |
--- 16 bits --

156 instructions from remaining * with 7 bits by reducing the address field

Total zero address instructions are =  156 * (2 ^ 7 ) = 19968

by (23 points)