Ace Test Series: Operating System - TLB Effective Access Time

Question

 

Comments

the given answer is correct !

By default we have to assume sequential access.

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@Shaik Masthan brother

How sequential by default it is hierarchical access of memory

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hierarchical or sequential are synonyms

parallel or simultaneous are synonyms

Answer 1

If you don't  assume hierchical structure, then it will be like

TLB1 access time+(miss rate of TLB1 * TLB2 access time)+(miss rate of TLB1 * miss rate of TLB2 *MAIN memory access time)

=10+0.9*20+0.9*0.8*1000=7228

Comments

What you have done is basically hierarical ,

One doubt Why you didnt take TLB search time ?

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In hierarchical we have to add sequential memory access time as access time. The formula will be hit rate of TLB 1*TLB1 access time+(miss rate of TLB1 * hit rate of TLB2(TLB1access time+TLB2 access time))+(miss rate of TLB1 * miss rate of TLB2 *(TLB1 access time +TLB2 access time +MAIN memory access time))

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Why didnt you add the TLB search time why only access time ?? any reason for that

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it is given that L1 and L2 for caches for most of the questions i have seen whenever they are talking about levels it refers to hiearachial structure :

you can use any formulae:

hit rate of L1 cache=h1

hit rate of L1 cache=h2

access time of L1 cache=t1

access time of L2 cache=t2

access time of MM=t3

 

h1*(t1)+(1-h1)*h2(t1+t2)+(1-h1)*(1-h2)*(t1+t2+t3)

or

t1+(1-h1)*{ t2+(1-h2)*t3 }

solving by 1:

0.1*10+0.9*0.2*(10+20)+0.9*0.8*(10+20+10000).       all units are in ns

=7228 ns

for 1000 logical address it will take 1000*7228ns==7228 micro sec

[P.S - answer will be 7228000 in ns please check the question again and correct me if i am wrong]

Answer 2

L1 hit + L1 miss then (L2 hit + L2 miss (Page Table access))

=> 0.1 (10) + 0.9(0.2*(10+20) + 0.8*(10+20+10000)) = 7228 ns