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True or False:In a uniform delay pipeline stage the execution time of a single instruction is equal to the time for execution of the instruction in non pipelined manner.

Shouldn’t it be false as thought each stage has uniform delay there would be additional buffer delay after each stage of the pipeline so shouldnt it be that it is not equal i.e it is more????

in CO and Architecture by Loyal (5.7k points) | 23 views
Yes, the statement is false unless it's given that the buffer latency is zero.
ya... I also thought that only but they have given it as true..

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