0 votes 0 votes A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3? CO and Architecture co-and-architecture branch-conditional-instructions speedup + – anjali007 asked Jan 23, 2019 • retagged Jul 17, 2022 by Shubham Sharma 2 anjali007 440 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 1 votes 1 votes As the branch is predicted at third stage, there will be 2 stall cycles. Speedup > 3 5 / (1+f*2) > 3 5 > 3+6f 6f < 2 f < 0.33 The probability that instruction being branch, so that the speed up is at least 3 is 0.33 balchandar reddy san answered Jan 23, 2019 • selected Jan 23, 2019 by anjali007 balchandar reddy san comment Share Follow See all 3 Comments See all 3 3 Comments reply anjali007 commented Jan 23, 2019 reply Follow Share Thanks... 0 votes 0 votes adarsh_1997 commented Jan 23, 2019 reply Follow Share @balchandar reddy san what exactly formula you used? 5/1+2p can you explain/ 0 votes 0 votes balchandar reddy san commented Jan 23, 2019 reply Follow Share Speedup is given as: Number of stages / (1 + dependency/branch instruction frequency * no.of stalls ) dependency/branch instructions in terms of probability ranging from 0-1. 0 votes 0 votes Please log in or register to add a comment.
