search
Log In
0 votes
60 views
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?
in CO and Architecture 60 views

1 Answer

1 vote
 
Best answer
As the branch is predicted at third stage, there will be 2 stall cycles.

Speedup > 3

5 / (1+f*2) > 3

5 > 3+6f

6f < 2

f < 0.33

The probability that instruction being branch, so that the speed up is at least 3 is 0.33

selected by
0
Thanks...
0

@balchandar reddy san what exactly formula you used?

5/1+2p can you explain/

0

Speedup is given as: 

Number of stages / (1 + dependency/branch instruction frequency *  no.of stalls )

dependency/branch instructions in terms of probability ranging from 0-1.

Related questions

3 votes
1 answer
1
298 views
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and $Y$ represent the number ... control data register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(
asked May 20, 2019 in CO and Architecture srestha 298 views
0 votes
2 answers
2
121 views
please provide a detailed solution
asked Feb 1, 2019 in CO and Architecture Vignaneswarkrishna 121 views
0 votes
0 answers
3
148 views
Consider the system which has virtual address of 36 bits and physical address of 30 bits and page size of 8 KB, page table entry contain 1 valid bit, 2 protection bit and 1 reference bit. Then the approximate page table size in (MB) is ________.
asked Jan 23, 2019 in CO and Architecture pream sagar 148 views
0 votes
0 answers
4
403 views
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4? A. 1.33 B. 1.76 C. 1.14 D. 1.66
asked Jan 23, 2019 in CO and Architecture Ram Swaroop 403 views
...